/**
 @file sys_usw_learning_aging.h

 @date 2010-3-16

 @version v2.0

---file comments----
*/

#ifndef _SYS_USW_LEARNING_AGING_H
#define _SYS_USW_LEARNING_AGING_H
#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_learning_aging.h"
#include "ctc_interrupt.h"
#include "ctc_register.h"
#include "sys_usw_common.h"

/***************************************************************
 *
 *  Defines and Macros
 *
 ***************************************************************/
struct sys_learning_aging_data_s
{
    mac_addr_t mac;

    uint16  fid;
    uint16  gport;
    uint16  cvlan;
    uint16  svlan;
    uint8   ether_oam_md_level;
    uint8   is_aging;
    uint8   is_ether_oam;
    uint8   is_logic_port;
    uint8   is_hw;
    uint32  key_index;
    uint32  ad_index;
};
typedef struct sys_learning_aging_data_s sys_learning_aging_data_t;

struct sys_learning_aging_info_s
{
    uint32 entry_num;
    sys_learning_aging_data_t* data;
};
typedef struct sys_learning_aging_info_s sys_learning_aging_info_t;

typedef int32 (* sys_learning_aging_fn_t)(sys_learning_aging_info_t* info);
typedef int32 (* p_aging_getptr_t)(uint8 lchip, uint8 domain_type, uint32 key_index, uint32* aging_ptr);


#define SYS_LEARNING_AGING_DBG_OUT(level, FMT, ...)                                           \
    {                                                                                         \
        CTC_DEBUG_OUT(l2, learning_aging, L2_LEARNING_AGING_SYS, level, FMT, ## __VA_ARGS__); \
    }

/**
   @brief struct type about aging info
 */

#define SYS_AGING_MAX_LEVEL 8

struct sys_aging_base_s
{
    uint32 aging_ptr_base[SYS_AGING_MAX_LEVEL];
    uint32 key_index_base[SYS_AGING_MAX_LEVEL];
    uint32 level_en[SYS_AGING_MAX_LEVEL];
    uint32 cam_ptr_base;
};
typedef struct sys_aging_base_s sys_aging_base_t;


struct sys_learning_aging_master_s
{
    uint32                   aging_max_ptr[SYS_AGING_TIMER_INDEX_MAX];
    uint32                   aging_min_ptr[SYS_AGING_TIMER_INDEX_MAX];

    sys_learning_aging_fn_t  hw_dma_cb;
    void                     * user_data;
    uint32                   is_hw_sync:1;
    uint32                   aging_tcam_num:20;
    uint32                   learning_disable:1;
    uint32                   rsv:10;

    sal_mutex_t*             p_aging_mutex;
    sys_aging_base_t         aging_base[SYS_AGING_DOMAIN_NUM];  
    p_aging_getptr_t         callbacks_get_ptr[SYS_AGING_DOMAIN_NUM];/*get aging ptr*/
    uint32 fib_free_ptr[SYS_AGING_MAX_LEVEL];
    uint32 level_index[SYS_AGING_MAX_LEVEL];
    ctc_l2_addr_t l2_addr;     /*for callback user cb*/
    ctc_learning_cache_t ctc_learning;
    ctc_aging_fifo_info_t ctc_aging;
};
typedef struct sys_learning_aging_master_s   sys_learning_aging_master_t;

/* ==============Arctic Start==============*/
    /*Arcitc
    LPM TCAM: 1024*20
    --------------------------   0
    lpm tcam
    --------------------------   20k
    total: 20,480 aging entry


    INTERNAL: 40,964*32
    --------------------------   0
    fibhost0 mac cam
    --------------------------   32
    internal 2R memory 000-001
    --------------------------   32 + 64k
    internal 2R memory 100-103
    --------------------------   32 + 64k + 576k = 32 + 640k
    internal 2R memory 104-105
    --------------------------   32 + 64k + 576k + 512k = 32 + 1152k
    internal 2R memory 106-107
    --------------------------   32 + 1152k + 64k
    fib host0 internal ip cam
    --------------------------   32 + 1152k + 64k + 32
    flow hash cam
    --------------------------   32 + 1152k + 64k + 32 + 32
    fib host1 cam
    --------------------------   32 + 1152k + 64k + 32 + 32 + 32
    internal 2R memory 200-201
    --------------------------   32 + 1152k + 64k + 32 + 32 + 32 + 32k
    internal 2R memory 205-208
    --------------------------   32 + 1152k + 64k + 32 + 32 + 32 + 32k + 32k
    total: 1,310,848 aging entry
    */
#define TCAM_AGING_NUM (20*1024)
#define SYS_AGIDX_BASE_MAC_CAM      0
#define SYS_AGIDX_BASE_MEMORY_000  (SYS_AGIDX_BASE_MAC_CAM + 32)
#define SYS_AGIDX_BASE_MEMORY_001  (SYS_AGIDX_BASE_MEMORY_000 + 32*1024)
#define SYS_AGIDX_BASE_MEMORY_100  (SYS_AGIDX_BASE_MEMORY_001 + 32*1024)
#define SYS_AGIDX_BASE_MEMORY_101  (SYS_AGIDX_BASE_MEMORY_100 + 96*1024)
#define SYS_AGIDX_BASE_MEMORY_102  (SYS_AGIDX_BASE_MEMORY_101 + 96*1024)
#define SYS_AGIDX_BASE_MEMORY_103  (SYS_AGIDX_BASE_MEMORY_102 + 192*1024)
#define SYS_AGIDX_BASE_MEMORY_104  (SYS_AGIDX_BASE_MEMORY_103 + 192*1024)
#define SYS_AGIDX_BASE_MEMORY_105  (SYS_AGIDX_BASE_MEMORY_104 + 256*1024)
#define SYS_AGIDX_BASE_MEMORY_106  (SYS_AGIDX_BASE_MEMORY_105 + 256*1024)
#define SYS_AGIDX_BASE_MEMORY_107  (SYS_AGIDX_BASE_MEMORY_106 + 32*1024)
#define SYS_AGIDX_BASE_HOST0_IP_CAM  (SYS_AGIDX_BASE_MEMORY_107 + 32*1024)
#define SYS_AGIDX_BASE_FLOW_HASH_CAM (SYS_AGIDX_BASE_HOST0_IP_CAM + 32)
#define SYS_AGIDX_BASE_HOST1_CAM     (SYS_AGIDX_BASE_FLOW_HASH_CAM + 32)
#define SYS_AGIDX_BASE_MEMORY_200  (SYS_AGIDX_BASE_HOST1_CAM + 32)
#define SYS_AGIDX_BASE_MEMORY_201  (SYS_AGIDX_BASE_MEMORY_200 + 16*1024)
#define SYS_AGIDX_BASE_MEMORY_205  (SYS_AGIDX_BASE_MEMORY_201 + 16*1024)
#define SYS_AGIDX_BASE_MEMORY_206  (SYS_AGIDX_BASE_MEMORY_205 + 8*1024)
#define SYS_AGIDX_BASE_MEMORY_207  (SYS_AGIDX_BASE_MEMORY_206 + 8*1024)
#define SYS_AGIDX_BASE_MEMORY_208  (SYS_AGIDX_BASE_MEMORY_207 + 8*1024)
/* ==============Arctic End==============*/


/***************************************************************
 *
 *  Functions
 *
 ***************************************************************/

/***************************************
 Learning module's sys interfaces
*****************************************/
extern int32
sys_usw_learning_set_action(uint8 lchip, ctc_learning_action_info_t* p_learning_action);

extern int32
sys_usw_learning_get_action(uint8 lchip, ctc_learning_action_info_t* p_learning_action);

/***************************************
 Aging module's sys interfaces
*****************************************/
extern int32
sys_usw_aging_set_property(uint8 lchip, ctc_aging_table_type_t tbl_type, ctc_aging_prop_t aging_prop, uint32 value);

extern int32
sys_usw_aging_get_property(uint8 lchip, ctc_aging_table_type_t tbl_type, ctc_aging_prop_t aging_prop, uint32* value);

extern int32
sys_usw_aging_set_aging_status(uint8 lchip, sys_aging_domain_type_t domain_type, uint32 key_index, uint8 timer, uint8 status);

extern int32
sys_usw_aging_set_aging_interval(uint8 lchip, uint8 timer_idx, uint32 age_seconds);

extern int32
sys_usw_aging_get_aging_ptr(uint8 lchip, uint8 domain_type, uint32 key_index, uint32* aging_ptr);

extern int32
sys_usw_learning_aging_sync_data(uint8 lchip, void* p_dma_info);

extern int32
sys_usw_aging_get_aging_status(uint8 lchip, sys_aging_domain_type_t domain_type, uint32 key_index, uint8* hit);

extern int32
sys_usw_aging_get_aging_timer(uint8 lchip, uint8 domain_type, uint32 key_index, uint8* p_timer);

extern int32
sys_usw_learning_aging_dump_db(uint8 lchip, sal_file_t dump_db_fp,ctc_global_dump_db_t* p_dump_param);

int32
sys_usw_learning_aging_set_hw_sync(uint8 lchip, uint8 b_sync);

/***************************************
 Init interfaces
*****************************************/
extern int32
sys_usw_learning_aging_init(uint8 lchip, ctc_learn_aging_global_cfg_t* cfg);

extern int32
sys_usw_learning_aging_deinit(uint8 lchip);

#ifdef __cplusplus
}
#endif

#endif /* !_SYS_USW_LEARNING_AGING_H */

